Recently, semiconductor memory devices increase steadily both in their integration degree and capacity. Research has been conducted for miniaturization of memory cells in a MOS dynamic RAM (DRAM) comprising a single MOSFET and a single MOS capacitor.
Due to the miniaturization of the memory cells, however, the area of the capacitor for storing information (electric charges) is reduced. As a result, soft errors such as misreading of the contents of the memory device or breakage of the contents of the memory device by .alpha.-rays have become problems to be solved.
Various methods have been proposed to increase integration degree and capacity while preventing the soft errors. In the methods, efforts have been made to substantially increase the capacity of the capacitor and hence a quantity of electric charges stored without increasing the area occupied by the capacitor.
One proposal is a DRAM having the following trench type capacitor structure.
A plan view and a cross-sectional view of such DRAM is shown in FIGS. 6(a) and 6(b). in which the DRAM comprises trenches 3 (3.sub.1, 3.sub.2, . . . ) formed in a surface of a p-type silicon substrate 1 and n-type layers 6 (6.sub.1, 6.sub.2, . . . ) formed on the inner walls of the trenches 5, capacitor insulator films 7 and plate electrodes 8 embedded in this order on the surfaces of the n-type layers to form capacitors. With this structure, the area (capacity) of the capacitor is increased without increasing the size of the capacitor.
Each MOSFET comprises source/drain regions 11 (11.sub.1, 11.sub.2, . . . ) and 12 (12.sub.1, 12.sub.2, . . . ) of an n-type layer and a gate electrode 10 (10.sub.1, 10.sub.2, . . . ), a gate insulator film 9 being formed between the source/drain regions 11 and 12 and the gate electrode 10, and formed within an element region defined by a field oxide film 3 which is formed on the surface of the silicon substrate 1. Each MOS capacitor comprises an n-type layer 6 disposed on the inner wall of an adjacent trench 5 and connected to the n-type layer source/drain region 11 (11.sub.1, 11.sub.2, . . . ) and 12 (12.sub.1, 12.sub.2, . . . ), a capacitor insulator film 7 formed on the surface of the n-type layer 6 and a plate electrode 8 embedded in the trench 5.
In this structure, the inner wall of the trench 5 is used to form the MOS capacitor. Therefore, the capacity of the capacitor is increased several times as large as that of a planar structure. Thus, this structure prevents a decrease in a quantity of electric charges stored in the memory cell even if the area occupied by the memory cell is reduced. Accordingly, this structure provides a small-sized DRAM having a large capacity of memory device.
With the above-described structure, however, as the distance between the trenches 5.sub.1 and 5.sub.2 of adjacent memory cells is reduced, stored electric charges (information) are likely to be lost by punch-through, which causes an error in the stored data.
This error occurs in a situation where information charges are stored in the n-type layer 6.sub.1 of one trench 5.sub.1 and no information charges are stored in the n-type layer 6.sub.2 of the other trench 5.sub.2. In such situation, the information charges stored in the n-type layer 6.sub.1 move to the other n-type layer 6.sub.2. As the depth of the trench increases, the error is more likely to occur. This is because as the trench becomes deeper, the length for the horizontal diffusion in the n-type layer 6 increases, so that the distance between adjacent n-type layers becomes relatively reduced.
Therefore, if a trench is, for example, 5 .mu.m deep, it is very difficult to reduce the distance between the adjacent trenches to 1.5 .mu.m or less.
This has become a big problem which prevents a further increase in the integration degree of DRAMs.
Referring to FIGS. 7(a)-7(c), (FIG. 7(b) is a cross-sectional view taken along the line 7(b)--7(b) of FIG. 7(a), and FIG. 7(c) is a cross-sectional view taken along the line 7(c)--7(c) of FIG. 7(a)), a structure is proposed in order to solve the above problem. In the structure, a capacitor is formed by sequentially forming a storage node electrode 6s, a capacitor insulator film 7 and a plate electrode 8 provided via an insulator film 20 on the inner wall of a trench 5 (Refer to Unexamined Japanese Patent Publication Sho 61-67954). The numeral 21 denotes an n-type layer which connects the storage node electrode 6s to an n-type layer 12 which constitutes the source/drain regions, and 31 denotes a bit line.
Each of the trench 5 and a storage node contact 42 which is formed in the insulator film 20 provided on the trench inner wall for connecting the n-type layer 21 to the storage node electrode 6s is disposed symmetrical with reference to the element region 51 surrounded by the element separating insulator film. FIG. 8 shows the positional relationship between an opening 743 in a mask pattern of the trench and an opening 742 in the storage node contact with respect to an opening 741 in a mask pattern f-or the element regions.
Since the trench inner wall is covered with the insulator film 20 in this structure, leakage due to punch-through is not likely to occur even if the distance between the adjacent trenches is reduced, which would otherwise occur between the n-type layers 6.sub.1 and 6.sub.2 as in the structure of FIG. 6.
However, leakage may possibly occur between a cell element region (source/drain region 12) and an adjacent n-type layer 21 which is formed in the trench inner wall and connects the storage node electrode 6S and the n-type layer 12 for the source/drain regions.
The storage node contact 42 which is formed in the insulator film 20 provided on the trench inner wall and connects the n-type layer 21 to the storage node electrode 6S is formed by patterning in the form of a very small hole. If a mask used for the patterning is misaligned, leakage is likely to occur.
As described above, there is a possibly of leakage between the n-type layer 21 and the element region (source and drain region 12) of an adjacent cell in the conventional trench type capacitor structure. Therefore, the distance t (FIG. 7(a)) between the storage node contact and the adjacent element region cannot be reduced greatly. Further, it is required very strict resolution and alignment in patterning the storage node contact.